As integrated circuit density and complexity increase, the need to reduce dimensions is paramount in achieving performance and yield goals. Multi-level metallization and overall design shrink become key to achieving the packing density necessary for VLSI and beyond.
One manufacturing requirement associated with multi-level metallization is topographical planarization. A relatively smooth planar or iso-planar surface is important for increasing metallization step coverage yields, and in feature size control. Additionally, the need for compatibility with the underlying aluminum alloy interconnect precludes any high temperature glass flow step in such planarizations.
In the process of forming a semiconductor wafer having two or more metal layers, a structure is produced prior to defining vias and depositing the second metal layer that comprises various layers of oxide, polysilicon conductors, and first metal conductors, all covered with a first interlevel dielectric (ILD1). Because the surface of the underlying structure is quite irregular, the surface of the interlevel dielectric ILD1 also is very irregular. If a second metal layer is applied directly on top of this interlevel dielectric, the sharp edges and crevices that tend to exist on the surface of the dielectric cause cracks in the second metal layer and result in incomplete metal coverage over the steps in the dielectric surface. Such defects reduce device yields.
A problem in double metal processes therefore has been to obtain a topographically planar or iso-planar surface prior to via definition and second metal deposition. Numerous methods have been attempted and used in the industry for such planarization of the interlevel dielectric.
One planarization method commonly used is to use a layer of photoresist material as a sacrificial layer. In this method, a layer of photoresist is applied over the interlevel dielectric. The photoresist is then etched back until the portions of the interlevel dielectric through which the vias are to be defined are revealed.
Problems have arisen in using a photoresist as a sacrificial layer because of the differences between the etch characteristics of the photoresist and the interlevel dielectric material. Because the photoresist is a polymer and the interlevel dielectric is typically a glass, during the etch-back process, the polymer photoresist tends to etch at a different rate than the interlevel dielectric, resulting in a less than ideally planar surface. Additionally, the etch material used is a plasma etcher, which causes the photoresist to polymerize further, coating the etching chamber with a polymer, and changing the etch characteristics of the polymer itself to provide a barrier to further etching, occasionally even halting the etching process altogether.
Other methods of planarization that have been attempted include surface leveling by RF sputter etching, and planarization using spun-on polyimide films.